The increasing use of MIDI and music synthesis capabilities in electronic musical instruments, Karaoke and PC multimedia applications is fueling the demand for high performance, yet cost effective, sound production systems. Digital sound synthesizing and processing systems make use of digital audio sample memory for a variety of purposes, including as a wavetable memory storing audio samples for synthesizing sounds, as a delay buffer memory for reverb and chorusing effects processing, and as a streaming audio memory receiving audio samples from external audio inputs such as a music keyboard, microphone, or the hard disk of multimedia PC. Such systems also employ a data cache memory in order to reduce the number of required accesses of the sample memory, and thereby minimize bottlenecks in this time-critical environment. One example of an audio signal processor integrated circuit architecture for music synthesis applications is described by Chris Deforeit et al., in a paper entitled "A Music Synthesizer Architecture which Integrates a Specialized DSP Core and a 16-bit Microprocessor on a Single Chip", presented at the 98th Convention of the Audio Engineering Society (AES) on Feb. 25, 1995. It has been embodied in the SAM9407 integrated sound studio circuit sold by Dream S.A. of Semur-en-Auxois, France, a subsidiary of Atmel Corporation of San Jose, Calif., the assignee of the present invention.
The aforementioned circuit architecture combines a synthesis digital signal processor (DSP) core, a control processor, a memory management unit, and peripheral I/O interface logic on a single chip. The synthesis DSP is constructed with hardware that has been optimized for the music synthesis task, and by repeatedly and efficiently performing a limited number of operations needed to carry out synthesis-specific algorithms, it directly generates and processes up to 64 simultaneous voices using the digital audio sample data accessed from external sample memory. The DSP synthesis algorithms are stored in on-chip program memory, while parameter data for the synthesized voices are stored in blocks of on-chip parameter memory. The control processor interfaces with external peripheral devices, such as a host computer or MIDI keyboard, through the peripheral I/O logic. The control processor parses and interprets incoming commands and data from such peripheral devices, and then controls the synthesis DSP by writing into the DSP's parameter memory. Besides these command parsing and control tasks, the control processor can also perform slowly changing synthesis operations, such as low frequency oscillation and waveform envelope management, by periodically updating synthesis parameters in the parameter memory. The memory management unit allows external memory resources to be shared by both the control processor and synthesis DSP. Thus, for example, a single external ROM device may serve as both program memory for the control processor and sample memory for the DSP, and a single external RAM device may serve as both external data memory for the control processor and delay buffer memory for the effects processing done by the DSP.
The synthesis DSP operates on a frame timing basis with each synthesis frame divided into several process slots (e.g., 64 slots in the aforementioned SAM 9407 device). A `process` relates to an elementary sound production function, such as one voice wavetable synthesis, one delay line for effects, etc., and each process generally involves reading or writing one or more audio samples from or to the digital audio sample memory. The maximum number of processes that can be executed within one synthesis frame (i.e., the number of slots) determines the capability of the device. For example, if all process slots were dedicated to wavetable synthesis, the number of slots would be the maximum polyphony (although slots might also be linked together to implement more complex synthesis algorithms). Also, some number of slots (e.g., eight) may be required for effects processing, leaving fewer slots available for polyphonic wavetable sound synthesis.
It is desirable to increase the number of processing slots per synthesis frame. Because each processing slot typically requires at least two digital audio sample memory accessed per frame, a 128 slot device would need 256 or more accesses per frame. With a state of the art frame rate of 48 kHz, this leads to sample memory cycles of at most 81 ns. Fortunately, in most cases, the same audio sample has to be accessed on successive frames. Thus, potential traffic bottlenecks between the synthesis DSP and the sample memory can be avoided by using an on-chip data cache memory to minimize the number of sample memory accesses that are needed. In a straightforward implementation, where the data cache has memory space for at least two audio samples allocated to each slot, the cache memory size in samples is at least twice the number of slots. With a typical audio sample width of about 16 or 24 bits, the data cache would need to hold a minimum of 4 or 6 kbits for a 128-slot device.
However, it is further desirable in a multimedia PC environment for the digital audio sample memory to share the PC's main memory instead of using separate ROM and RAM. But, the structure of modern PC buses (such as PCI) uses a memory word width of 256 bits (referred to as a PC cache line). Thus, a regular implementation of a synthesis DSP's data cache memory usable in such a PC memory sharing environment would require two PC cache lines per processing slot, and hence a size of at least 64 kbits of on-chip cache for a 128-slot device.
It is an object of the present invention to implement an improvement in cache memory organization for sound synthesis DSP applications that results in a significant reduction in the required size of the data cache memory.
It is another object of the present invention to optimize the synthesis DSP cache management to the large cache line structure of modern PC buses in order to improve transfers of audio sample data between the sample memory located on the PC's main board and the on-chip data cache memory.
It is a further object of the invention to provide for variable digital audio sample memory word sizes.